1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a field device transistor.
2. Description of Related Art
Electrostatic discharge (EDS) has been one of the major causes of damage to integrated circuits in semiconductor fabrication process. In a deep sub-micron integrated circuit, the degree to which EDS causes the malfunction of an integrated circuit is even more serious and may result in damage to the circuit. In order to overcome the problems caused by the EDS, an on-chip EDS protection circuit is added to the pads at the output end and input end of a complement metal-oxide-semiconductor (CMOS). However, because of to the progress in the field of semiconductor fabrication, the protection provided by the EDS protection circuit no longer meets the real need.
A conventional ESD protection circuit including a field device transistor is shown in FIG. 1. Referring to FIG. 1, static voltage or over-stress voltage at the input port I/P is discharged through the field device transistor 10 to the ground V.sub.SS. The input buffer gate 12 and the internal circuit 14 are under the protection of the field device transistor 10.
A schematic, cross-sectional view of the field device transistor 10 in FIG. 1 is shown in FIG. 2. Referring to FIG. 2, a conventional field device transistor includes a gate 25, a source region 22 and a drain region 23 formed on a substrate 20, and a field oxide layer 24 located between the source region 22 and the drain region 23. For a N-type field device transistor, a heavily doped P-type region 26 is formed under the field oxide layer 24. The source region 22 is grounded by connected to a ground V.sub.SS (FIG. 1) through an interconnect 27. In the meantime, the gate and the drain region 23 are connected to the input port I/P and the buffer input gate 12 in FIG. 1 through the interconnect 27 in order to protect the internal circuit 14 from ESD and over-stress voltage.
When an over-stress voltage signal appears at the input port I/P, the field device 10 bypasses the over-stress voltage signal by applying a punch-through effect. Since the punch-through effect on the field device transistor 10 acts faster than the junction breakdown thereon according to a over-stress voltage signal, the field device transistor 10 can be used as a protection to prevent breakdown from occurring on low-voltage gate oxide layers in the internal circuit.
However, a heavy P-type implantation process is conventionally used to improve the isolation between devices. The heavy P-type implantation also forms a P-type heavily doped region 26 located underneath the field oxide 24 of the field device transistor 10. Hence, the threshold voltage V.sub.T of the field device transistor 10 is normally as high as about 12 to 14 volts. For a gate oxide layer whose thickness is below 50 .ANG., which gate oxide layer normally has a breakdown voltage of about 5 to 6 volts, a conventional field device transistor 10 cannot provide sufficient protection.